1. Field of the Invention
The present invention relates in general to a signal transfer circuit for a synchronous memory device, and more particularly to a signal transfer circuit which is capable of reducing a delay time to transfer an internal address signal at high speed synchronously with a clock signal in a burst mode and of transferring the internal address signal even at a short period of the clock signal.
2. Description of the Prior Art
Generally, semiconductor memory devices such as a synchronous dynamic random access memory (synchronous DRAM or SDRAM) are used synchronously with a clock signal. Such a semiconductor memory device receives the clock signal when a clock enable signal is made active and then processes external input signals synchronously with the received clock signal.
Referring to FIG. 1, there is shown a circuit diagram of a conventional signal transfer circuit for a synchronous memory device. As shown in this drawing, the conventional signal transfer circuit comprises a multiplexing circuit 11 for receiving an external address signal add.sub.-- ext and an internal address signal add.sub.-- int from an address counter circuit (not shown). The multiplexing circuit 11 transfers the received external address signal add.sub.-- axt to an internal circuit 12 in a first mode and it transfers the received internal address signal add.sub.-- int to the internal circuit 12 in a second mode. The internal circuit 12 is adapted to generate a data signal in response to the external or internal address signal add.sub.-- ext or add.sub.-- int transferred by the multiplexing circuit 11 and to transfer the generated data signal to a data output buffer 13. The data output buffer 13 is adapted to buffer the data signal transferred by the internal circuit 12 and to output the buffered data signal externally.
The conventional signal transfer circuit further comprises a multiplexing controller 14 for generating first and second mode control signals in response to a clock signal clk and applying the generated first and second mode control signals to the multiplexing circuit 11, and an output buffer controller 15 for generating an output buffer control signal in response to the clock signal clk and applying the generated output buffer control signal to the data output buffer 13.
The operation of the conventional signal transfer circuit for the synchronous memory device with the above-mentioned construction will hereinafter be described.
The multiplexing controller 14 includes a delay circuit connected between nodes N5 and N7, a NAND gate G3 and an inverter connected in series between the nodes N5 and N7 and a node N8, a first transfer transistor circuit connected between the node N8 and a node N9, and a second transfer transistor circuit connected between the node N8 and a node N10. The first transfer transistor circuit is provided with NMOS and PMOS transistors MN4 and MP4 connected in parallel between the node N8 and the node N9. The second transfer transistor circuit is provided with NMOS and PMOS transistors MN5 and MP5 connected in parallel between the node N8 and the node N10. The delay circuit is provided with three inverters connected in series between the nodes N5 and N7. If the clock signal clk is applied to an input terminal, it is delayed by a predetermined time period through the three inverters connected in series between the nodes N5 and N7 and the supplied to the NAND gate G3. The NAND gate G3 NANDs the delayed clock signal from the three inverters and the clock signal clk from the input terminal. The NANDed result from the NAND gate G3 is inverted by another inverter and then transferred to the multiplexing circuit 11 through the first and second transfer transistor circuits which are operated in response to a control signal sig1.
The multiplexing circuit 11 includes a first transfer transistor circuit for transferring the external address signal add.sub.-- ext to the internal circuit 12, and a second transfer transistor circuit for transferring the internal address signal add.sub.-- int from the address counter circuit to the internal circuit 12. The first transfer transistor circuit is provided with PMOS and NMOS transistors MP1 and MN1 which are operated in response to the first output signal from the multiplexing controller 14. The second transfer transistor circuit is provided with PMOS and NMOS transistors MP2 and MN2 which are operated in response to the second output signal from the multiplexing controller 14.
If the external address signal add.sub.-- ext is applied to a node N1, the multiplexing controller 14 provides its output signal to the output node N9 to turn on the NMOS and PMOS transistors MN1 and MP1 in the multiplexing circuit 11. As a result, the external address signal add.sub.-- ext from the node N1 is transferred to a node N3 through the turned on NMOS and PMOS transistors MN1 and MP1. In a burst mode employing the internal address signal add.sub.-- int from the address counter circuit, the multiplexing controller 14 provides its output signal to the output node N10 to turn on the NMOS and PMOS transistors MN2 and MP2 in the multiplexing circuit 11. As a result, the internal address signal add.sub.-- int from a node N2 is transferred to the node N3 through the turned on NMOS and PMOS transistors MN2 and MP2. The address signal transferred to the node N3 is then applied to the internal circuit 12 which generates a data signal in response to the applied address signal and transfers the generated data signal to the data output buffer 13.
The data output buffer 13 is adapted to output the data signal transferred by the internal circuit 12 to an output terminal N13 in response to a pulse signal from the output buffer controller 15. To this end, the data output buffer 13 includes a pull-up transistor MP3 connected between a supply voltage source Vdd and an output node N13, a pull-down transistor MN3 connected between the output node N13 and a ground voltage source Vss, and NAND gate G1 for NANDing the data signal from the internal circuit 12 and the pulse signal from the output buffer controller 15 and supplying the NANDed result to a gate terminal of the pull-up transistor MP3, and a NOR gate for NORing the data signal from the internal circuit 12 and an inverted one of the pulse signal from the output buffer controller 15 and supplying the NORed result to a gate terminal of the pull-down transistor MN3.
The output buffer controller 15 is adapted to apply the pulse signal to a node N6 in response to the clock signal clk to control the operation of the data output buffer 13.
On the other hand, the external address signal add.sub.-- ext is applied in the initial mode and the internal address signal add.sub.-- int from the address counter circuit is applied in the burst mode.
Noticeably, the data access time in the initial mode that the external address signal add.sub.-- ext is applied is the same as that in the subsequent mode or burst mode that the internal address signal add.sub.-- int from the address counter circuit is applied. Namely, the data accessing operation is performed in response to the same clock signal in the initial mode and the burst mode. The data accessing operation will hereinafter be described in more detail with reference to FIG. 2.
FIG. 2 is a timing diagram illustrating the operation of the conventional signal transfer circuit in FIG. 1. In this drawing, the reference character ya designates the output address signal from the multiplexing circuit 11, the reference character dly1 designates a delay time required in outputting data to the output terminal in response to the external address signal add.sub.-- ext, and the reference character dly2 designates a delay time required in outputting data to the output terminal in response to the internal address signal add.sub.-- int.
As seen from FIG. 2, the delay time dly1 and the delay time dly2 are the same. In other words, in the initial mode that the external address signal add.sub.-- ext is applied and in the burst mode that the internal address signal add.sub.-- int from the address counter circuit is applied, data are outputted after the same time from the moment that the clock signal clk is made active.
For this reason, in the burst mode that the internal address signal add.sub.-- int from the address counter circuit is applied, the delay time required in outputting data in response to the clock signal clk is excessively long, resulting in a degradation in operation speed. Further, in the case where the clock signal clk has a short period, a faulty operation may be caused because of the long delay time.